TSMC's test chip for the 5nm process has two types, one is 256Mb SRAM, and the unit area includes a high-current version of 25,000 square nanometers and a high-density version of 21,000 square nanometers, which claims to be the smallest to date with a total area of 5.376 square millimeters.
The second is the integration of SRAM, CPU\/GPU logical unit, IO unit, the area ratio is 30%, 60%, 10%, the total area is estimated to be about 17.92 square millimeters.
The 5-nanometer chip means that the distance between the two transistors is 5 nanometers, and the value of a nanometer is equal to 1\/10 billion meters