1, surface cleaning
< br >
2, primary oxidation
< br >
3. A layer of Si3N4 (Hot CVD or LPCVD) is deposited by Chemical Vapor deposition (CVD) method. (1) Normal Pressure CVD (2) Low Pressure CVD (3) Hot CVD (Hot CVD)\/(thermal CVD) (4) Plasma enhanced CVD Enhanced CVD) (5) MOCVD (Metal Organic CVD) & Enhanced CVD) (5) MOCVD (Metal Organic CVD) & AMP; Molecular Beam Epitaxy (6) (LPE)
< br >
4. Coating the photoresist (1) coating of the photoresist (2) pre bake (3) exposure (4) development (5) post bake (6) etching (7) removal of the photoresist;
< br >
5. Silicon nitride is removed by dry oxidation here.
< br >
6, ion planting boron ions (B3) are injected into the substrate through SiO2 film to form a P-type trap.
< br >
7, remove the photoresist, put high temperature furnace for annealing treatment.
< br >
8. The silicon nitride layer is removed with hot phosphoric acid and doped with phosphorus (P 5) ion to form an N-type trap.
< br >
9, annealing treatment, and then use HF to remove SiO2 layer
< br >
10, a layer of SiO2 layer is generated by dry oxidation method, and then a layer of silicon nitride is deposited by LPCVD.
< br >
11, the use of lithography technology and ion etching technology to retain the silicon nitride layer above the lower gate isolation layer.
< br >
12, wet oxidation, the growth of SiO2 layer without silicon nitride protection, forming an isolation area between PN;
< br >
13, hot phosphoric acid removal of silicon nitride, and then use HF solution to remove the gate isolation layer of SiO2, and re-generate a better quality SiO2 film, as the gate oxide layer.
< br >
14, LPCVD deposited polysilicon layer, and then coated with photoresist for photolithography, as well as plasma etching technology, gate structure, and oxidation to generate SiO2 protective layer.
< br >
15. The surface is coated with photoresist, the photoresist in the P-well region is removed, and arsenic (As) ions are injected to form the source drain of NMOS. In the same way, in the N-well region, B ions are injected to form the source drain of PMOS.
< br >
16. PECVD is used to deposit a layer of undoped oxide layer to protect the components and perform annealing treatment.
< br >
17, deposition doped boron and phosphorus oxide layer 18, sputtering the first layer of metal (1) film deposition method varies according to its use, the thickness is usually less than 1um. (2) Evaporation Deposition (3) Sputtering Deposition (2) evaporation deposition & NBSP;
< br >
19. Lithography determines VIA holes, deposits a second layer of metal, and etches the connecting structure. Then, PECVD oxidation layer and silicon nitride protective layer are used.
< br >
20, lithography and ion etching, determine the PAD position.
< br >
21, finally annealing treatment to ensure the integrity of the entire Chip and the connectivity of the wire
1. Pre-finishing grinding: wash and clean the raw material wafer, grinding to remove surface contamination.
2. Wafer fusing: The raw material wafer is divided into many small pieces in order to better fuse into the appropriate size.
3. Coating thick film: Coating the film with accurate thickness, controlling the thickness and appearance of the layer.
4. Corrosion: passivation corrosion to remove excess film layer.
5. Lithography: Etching specific shapes and patterns on the wafer surface.
6. Gold plating: Add a thin film on the wafer surface to improve its electrical conductivity.
7. Burn: Burn the circuit on the wafer to complete the final circuit design.
8. Test: The wafer performance test and inspection.
9. Package: Package the wafer to make it a usable integrated circuit product.