1, K read-only memory EPROM. The data will not be lost after the power failure, and during the operation of the microcomputer system, it can only be read, but not written, a class of memory for storing fixed data.
2, the role of the chip: common chips are: CP...
The output of the two 74LS138 pieces is respectively a 4-wire to 16-wire decoder (8) connected by two 74LS138 pieces in Figure 9, indicating that the (1) piece 74LS138 works and the (2) piece 74LS138 is prohibited, and the 8 codes of 0000 ~ 0111 are translated into 8 low-level signals.
< Example 2] Try two 3-8-line decoder 74LS138 to form a 4-16-line decoder, and translate the input 4-bit binary code into 16 independent low-level signals. Solution: As shown in Figure 8, 74LThe S138 has only three address inputs.If the output is not gated, the default is high. In summary, D3-D5 selects one of the following eight 74LS138 pieces to work, and D0-D2 makes the 74SL138 in working state output a value. In this way, the 6-64 decoder composed of 9 74LS138 is realized. The output of the
or gate is used as the carry output of the adder. That is, the design of the adder is completed. Back to the analysis: when the adder inputs are: a=1, b=0, ci=1.As shown in Figure 8, 74LS138 has only three address input terminals. If you want to use 4-bit binary code, you can only use an additional control terminal (one of them) as the fourth address input.
A 3-8-line decoder 74LS138 can be used to form any three-variable input logic function, any input three-variable logic function can be used a 3-8-line decoder 74LS138 to achieve.
1, do not understand your problem, the 16-bit address bus can address 64KB, assuming that only 4K*8B, only choose a 2716 and two 2114.
2, the curing area is a chip 2k*8 bits, read-only can not be written (R/W line can only keep reading can not be turned into write signal). The work area requires you to use several 1k* 4-bit chips to form 2k* 8-bit, a total of 16 address buses, and 1 control busThe R/W lines ask you to draw the structure. It's too complicated, so draw it yourself.
3, K refers to 2K storage units (not necessarily bytes), 8 means that each storage unit is 8 binary bits.
4, the capacity is 2048×8bit. There are eight address lines D0 to D7. There are 11 address lines A0 to A10.
5, this question is very simple, because the number of digits is the same, one is 4K needs 64K 64÷4=16.
6, draw the CPU and memory connection diagram, requirements: (1The memory chip address space is allocated as follows: the maximum 4K address space is the system program area, the adjacent 4K address space is the system program work area, and the minimum 16K address space is the user program area; (2) Indicate the type and number of selected memory chips; (3) Draw the film selection logic in detail.
[Answer] : The commonly used EPROM chip is 2712732762712272527512, where 27 is the code name of the EPROM chip, and the last two digits represent the memory capacity of the EPROM. For example, the 64 of 2764 stands for 64 KB (bit).
EPROM chip: 2764 storage capacity is 8K (8K*8bit) 27128 storage capacity is 16K (16K*8bit) 27256 storage capacity is 32K (32K*8bit) EInvented by Israeli engineer Dov Frohman, PROM is a computer memory chip that retains data after a power outage-that is, non-volatile (non-volatile).
If it is necessary to burn the software code is long, the on-chip program memory space is limited, should expand the external ROM (program memory), the maximum can be extended to 64k bytes, commonly used chips have 2764,27128,27256,27512, etc., their storage space is 8k, 16k, 32k, etc. 64k bytes.
ROM chip: (27-EPROM) 2716 (2K×8), 2732 (4K×8), 2764 (8K×8), 27128 (16K×8), 27256 (32K×8), 27512 (64K×8), etc. (28-EEPROM) : 2816 (2K×8), 2864 (8K×8).
. The main memory capacity of a machine is 2MB. If byte addressing is used, the address line must be ___21__ bits. 13. The control memory in a microprogrammed computer is used to store the ___ microcommands ___. 14. A common soft copy output device is the ___ monitor ___.
A to address the 4KB range requires 12 lines, A0~A11 is connected to the CPU A0~A11, used for ROM addressing. The A12~A14 of the CPU is connected to the 38 decoder to generate the slice selection signal.
Memory capacity calculation problem ROM area 3000H~4FFFH, so the ROM area capacity is 5000H, 3000H = 2000H, that is, 8kByte. The RAM area is 5000H to 67FFH, so the RAM area capacity is 6800H-5000H = 1800H, that is, 6kByte.