DFT engineers are Design for Testability (DFT) engineers who are primarily responsible for the design and testing of integrated circuits (ics). Majors in this field usually involve electrical engineering, computer science, microelectronics and other related fields.
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The work of DFT engineers mainly includes the following aspects:
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1. Design and integrate chip-level DFT solutions, including SCAN, MBIST and JTAG.
2. Responsible for the automatic generation and simulation of DFT test vector.
3. Work closely with logic design engineers to improve DFT test coverage.
4. Work closely with product engineers and test engineers to debug and resolve DFT test vectors that fail on the test machine.
5. Participate in chip DFT architecture definition and design.
6. Complete DFT circuit design, including Scan, Mbist, Bscan, etc.
7. Assisted the back-end team to deal with timing analysis and timing convergence related to DFT.
8. Use EDA tools to generate test vectors and conduct simulation verification.
9. Participate in ATE, debug test failure.
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Therefore, the knowledge and skills required to become a DFT engineer include, but are not limited to:
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1. Familiar with RTL design.
2. Familiar with the clock reset network of the whole design.
3. Familiar with timing constraints in DFT mode, assist design engineers to generate SDC with timing constraints and complete timing convergence in DFT mode.
4. Proficient in tcl, perl, makefile and other scripting languages.
5. Have experience in using Designcompiler, Formality, Mentor tessent and other EDA tools.
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If you are interested in becoming a DFT engineer, consider enrolling in a relevant university or postgraduate course, or looking for internships and jobs to gain practical experience and improve your skills.