The 74HC138 is a high-speed CMOS device with the 74HC138 pin compatible with the low power Schottky TTL (LSTTL) family. The 74HC138 decoder accepts 3-bit binary weighted address inputs (A0, A1, and A2) and, when enabled, provides 8 mutually exclusive low-significant outputs (Y0 to Y7).
The 74HC138 features three enable inputs: two low effective (E1 and E2) and one high effective (E3). Unless E1 and E2 are set low and E3 is set high, 74HC138 will keep all outputs high.