First, stacked 14nm chipsets need to deliver similar power efficiency and power consumption as 7nm chips. Typically, a 14nm chip needs to at least double its power consumption to reach the performance level of 7nm, while further expanding the chip area to accommodate more transistors. This will result in the size of the chip becoming larger and difficult to adapt to the small size requirements of current mobile devices.
Second, chip stacking technology also presents challenges in terms of thermal management. Stacked chips will increase the concentration of heat, resulting in more difficult heat dissipation, which can easily lead to overheating of the chip and affect performance and life. Therefore, it is necessary to design and apply efficient cooling systems to solve this problem.
In addition, chip stacking technology also has higher requirements for electrical interconnection. A stable electrical connection needs to be maintained between the stacked chips to ensure the stability and speed of data transmission. This puts forward higher requirements for the design and process of the chip, and needs to solve the problems of signal interference and electromagnetic compatibility.
The 7nm chip refers to the size of the transistor, which is much smaller than the size of the 14nm chip. Therefore, it is not feasible to superimpose two 14nm chips into a 7nm chip because the component size of a 14nm chip is much larger than that of a 7nm chip.
In addition, the manufacturing process of 7nm chips is also more complex than that of 14nm chips, so 14nm chips do not have the ability to manufacture 7nm chips. Finally, 7nm chips must use high-precision lithography technology, and 14nm chips do not have this technology. Therefore, it is not feasible to superimpose 14nm chips into 7nm chips.