Now the mainstream integrated circuit device is still CMOS, so the theoretical structure is still based on CMOS. CMOS has two MOS combinations of N and P. The simplest CMOS device is the inverter. Then there is the standard logic gate (and gate or gate), the standard unit is composed of and gate and or gate using w\/L= 2:1 PMOS and NMOS. Then, all the digital logic can be implemented. Of course, in practical applications, there are some other important structures, but these three units are basic.
Logic gate:
To construct a logic gate, you need to determine the inputs and outputs, and then use the NMOS topology and PMOS topology to construct the logic gate. Here, because the connection relationship between NMOS and PMOS generally adopts the dual relationship (series pair parallel, parallel pair series), only one topology is needed to get the function achieved by the logic gate. Take NMOS as an example: series is and, parallel is or, and the final output can be added not. Other multi-input models are also designed based on this.
transfer characteristic
As mentioned earlier, series is and, parallel is or. This is based on switching devices. In the actual MOS device, the series structure has a delay. For example, two inputs A and B, A is above B, that is, A is near the output. At A=0, B=0, F outputs a high voltage. When A is high, NMOS-A acts as a resistance and can decrease rapidly. When B is high, NMOS-B acts as a resistance, and NMOS-A is equivalent to adding a pull-down resistance, which takes longer to turn on. So A=1, B=0-> The delay of 1 is greater than B=1, A=0-> The delay of 1 is smaller. The distinction is made here with the two doors of the door.
The most direct result of this delay is to limit the number of inputs. If you fan in too much, the delay will increase to unacceptable levels. It is also possible that the top MOS gate voltage is greater than the supply voltage and fails. Generally, the number of input is less than or equal to 4.
For more input devices, the method of unit circuit combination can be used. The delay of this implementation method will be converted into multiple paths, where the slowest path is the speed of the circuit. The analysis here is to consider logical effort.
logical effort
Computational logic strives to have software that can be simulated, and for estimation, it is easier to understand using the inverter model.
In general design, the W\/L value of MOS is determined. So for a inverter, the delay is also certain. The total delay of the ideal inverter Di=tp0 (1 fi), and we generally use Di=tp0 (p gi hi).
Here tp0 acts as a unit delay, and the length of m is a concept. P is the delay of the input capacitance, which is used to describe the input delay, and is the delay of this circuit when it is unloaded. g is the number of equivalent inverters, or logical effort. h is Cout\/Cin, which is fan-out. Obviously, the larger the fanout, the larger the series that can be accommodated, and the larger the delay. Here is the calculation of these parameters:
g, divide the width to length ratio of the series by the number of series, parallel does not change, the sum divided by 2 is the denominator, the numerator is the sum divided by 2; Simple understanding is that the series delay increases, reflected in the denominator reduction correction. A 2:1 inverter is generally used here as the standard.
It refers to the basic logic gate manufactured by CMOS technology, which commonly includes AND gate, OR gate, NOT gate, NAND gate, NOR gate, XOR gate and XNOR gate, etc.
These gates have the advantages of low power consumption, high noise tolerance and high reliability, and are widely used in digital circuits.
Refers to the basic logic gate circuit manufactured by CMOS technology, including AND gate (AND), OR gate (OR), NOT gate (NOT), XOR gate (XOR), etc.
CMOS technology is a commonly used integrated circuit manufacturing technology that utilizes the complementary properties of P-type and N-type MOS (Metal-Oxide-Semiconductor) transistors. In CMOS digital integrated circuits, each logic gate consists of a pair of complementary MOS transistors.
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Standard gate circuits are characterized by their fixed logic functions and input\/output characteristics, and can be used to build more complex digital logic circuits. For example:
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- AND gate (AND) : has two or more inputs and outputs are logically high only if all inputs are logically high.
- OR gate (OR) : Has two or more inputs. As long as one input is logically high, the output is logically high.
- NOT: Has an input whose output is the opposite of the input, i.e. when the input is logically high, the output is logically low, and vice versa.
XOR gate (XOR) : has two inputs, when the two inputs are different, the output is a logic high level; When the two inputs are the same, the output is logically low.
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Standard gate circuit is the basic building block of digital logic circuit design. By combining and connecting different standard gate circuits, various complex digital functions and algorithms can be realized.