DDR chip testing is carried out both in the initial chip stage and in the final package stage. The tester used is usually a memory automatic test device, and its value is generally more than millions of dollars. The core part of the tester is a programmable high resolution signal generator. Test engineers use programming to simulate the actual working environment; In addition, he can also fine-tune the edge of the timing pulse to find the balance point.
The automatic tester (ATE) system is also flawed. The arbitrary number of waveforms it produces is limited by its own backup image random memory and algorithm generator. Due to the limitation of the random memory depth of the image, the waveform can only be repeated within its own loop. Because DDR bandwidth and speed are twice as high as normal SDRS, the waveform variation should also be twice as high. Therefore, the image random memory capacity of the tester is quickly consumed. Therefore, to ensure a certain test resolution, it is necessary to increase the memory of the tester.
Setting up a test head is also a tricky problem. Because the data read window of DDR memory is only 1-2ns, the rise and fall times of pin drives are critical. In order to ensure the signal conversion in the center of the data eye, a good pin driver steering speed is required.
At 266MHz, transmission line reflections begin to appear. Design engineers find that they must follow the linear law when designing test platforms. In order to ensure the uniformity of the signal, it is necessary to simulate the transmission line layout of the test head. Pin driver strength must minimize high frequency signal reflection.