Simply put, the chip design, the early implementation of the function and then simulation, can be written with verilog, the version out of the need to first use FPGA to verify the function, when the function verification is completed, the code needs to be transplanted to the ASIC, made into a netlist, and then the stream chip, so that the new chip is designed. Therefore, the early stage of chip design and FPGA work is similar. FPGA design only focuses on functional simulation and implementation in FPGA, without the need to make ASIC. Chip designers and FPGA designers can be classified into the logic design section.