Chip design is divided into front-end design and back-end design, front-end design (also known as logic design) and back-end design (also known as physical design) and there is no unified strict boundary, involving the design related to the process is the back-end design.
Front-end design process:
1. Specification development
The chip specification, like the feature list, is the design requirements that the customer puts forward to the chip design company (called Fabless), including the specific functions and performance requirements that the chip needs to achieve.
2. Detailed design
According to the specifications proposed by customers, Fabless comes up with design solutions and specific implementation architecture, and divides module functions.
3. HDL coding
The use of hardware description language (VHDL, Verilog HDL, industry companies generally use the latter) to describe the module function in code, that is, the actual hardware circuit function is described through the HDL language, forming RTL (register transfer level) code.
4. Simulation verification
Simulation verification is to check the correctness of the coding design, and the test standard is the specification formulated in the first step. See if the design accurately meets all the requirements in the specification. Specifications are the gold standard of correct design, all violations, do not meet the requirements of the specifications, you need to modify the design and coding. Design and simulation validation is an iterative process until the validation results show full compliance with the specifications.
VCS for the simulation verification tool Synopsys, and NC-Verilog for Cadence.
5. Logic synthesis -- Design Compiler
The simulation verification is passed and logic synthesis is carried out. The result of logical synthesis is to translate the designed HDL code into a gate level netlist. Synthesis needs to set constraints, that is, the standard that you want the synthesized circuit to achieve in terms of target parameters such as area and timing. Logic synthesis needs to be based on a specific comprehensive library, and in different libraries, the area and timing parameters of the basic standard cell of the gate circuit are different. Therefore, the selected comprehensive library is not the same, and the synthesized circuit is different in timing and area. In general, after the synthesis is completed, the simulation verification needs to be done again (this is also called post-simulation, and the previous is called pre-simulation).
Logic synthesis tool Synopsys Design Compiler.
6. STA
Static Timing Analysis (STA), static timing analysis, which also belongs to the category of verification, it is mainly in the timing to verify the circuit, check whether there is a violation of the setup time and hold time. This is the basic knowledge of digital circuit, when a register appears these two timing violations, there is no way to correctly sample data and output data, so the register-based digital chip function will certainly have problems.
The STA tool has Synopsys Prime Time.
7. Formal verification
This is also the validation category, which is functionally (STA is timing) to verify the integrated netlist. The commonly used method is equivalence checking, which takes the HDL design after functional verification as a reference and compares the synthesized netlist functions to see whether they are functionally equivalent. This is done to ensure that the circuit function originally described by HDL is not changed during the logic synthesis process.
The Formality validation tool is Synopsys Formality
Back-end design process:
1. DFT
Design For Test. Design for test. Chips often have built-in test circuits, and the purpose of DFT is to design with future tests in mind. A common approach to DFT is to insert a scan chain into the design to turn non-scan units (such as registers) into scan units. Some books have detailed information about the DFT, and it is easy to understand it by comparing the pictures.
DFT Tool Synopsys DFT Compiler
2. FloorPlan
Layout planning is to place the macro unit modules of the chip, in general to determine the placement of various functional circuits, such as IP modules, RAM, I\/O pins, and so on. Layout planning can directly affect the final area of the chip.
The tool is Astro from Synopsys
3. CTS
Clock Tree Synthesis, clock tree synthesis, simply put, is the clock wiring. Due to the global command role of the clock signal in the digital chip, its distribution should be symmetrical connected to each register unit, so that the clock from the same clock source to each register, the clock delay difference is minimal. This is why the clock signal needs to be wired separately.
CTS tool, Synopsys Physical Compiler
4. Wiring (Place & Route)
The wiring here is the ordinary signal wiring, including the wiring between various standard units (basic logic gate circuits). For example, the 0.13um process we usually hear, or the 90nm process, is actually the minimum width that can be achieved by the metal wiring here, which is the channel length of the MOS tube from a microscopic point of view.
Tool Synopsys for Astro
5. Parasitic parameter extraction
Due to the resistance of the wire itself, mutual inductance between adjacent wires, coupling capacitors will produce signal noise, crosstalk and reflection inside the chip. These effects can cause signal integrity problems, resulting in signal voltage fluctuations and changes, and, if severe, signal distortion errors. It is very important to extract parasitic parameters and analyze the signal integrity problem again.
Tool Synopsys Star-RCXT
6. Layout physical verification
Verify the function and timing of the physical Layout of the wiring. There are many verification projects, such as the verification of LVS (Layout Vs Schematic), which is simply the comparison and verification of the gate-level circuit diagram after the layout and logic synthesis. DRC (Design Rule Checking) : design Rule Checking to check whether the cable spacing and cable width meet the process requirements; ERC (Electrical Rule Checking) : electrical rule checking to check short circuit and open circuit violations; Let's wait.
The tool is Hercules for Synopsys
The actual back-end process also includes circuit power analysis, as well as DFM (Design for Manufacturability) issues that arise as manufacturing processes continue to advance, not to mention here.
The completion of the physical layout verification is the completion of the entire chip design phase, and the following is the chip manufacturing. The physical layout is handed over to the chip Foundry (called Foundry) in the GDS II file format to make the actual circuit on the wafer, and then packaged and tested, and we get the chip we actually see