Logic chip is also called programmable logic device, English PLD. PLD is produced as a general integrated circuit, and its logic function is determined according to the user's device programming. The integration degree of general PLD is high enough to meet the needs of designing general digital systems.
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Memory chip is the specific application of the concept of embedded system chip in the storage industry. Therefore, whether it is a system chip or a memory chip, it is by embedding software in a single chip to achieve multi-function and high performance, as well as support for multiple protocols, multiple hardware and different applications.
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The difference between logic chips and memory chips
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The process of logic chips is still around 20nm, such as Intel's CPU, and memory chips have approached 10nm, such as flash memory, what is the difference between the two?
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1) Difference: The difference between the two chip processes is mainly caused by the difference in the structure\/working mode of the core component of the two chips - the transistor, which can be referred to the semiconductor device related books and papers.
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2) Size: From the gate length indicator, you are right, 2D NAND Flash uncontacted poly half pitch is currently better than 14\/16nm FINFET Lg. According to ITRS 2015 data, the former is 15nm and the latter is 24nm. [1]
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3) Naming: However, it should be noted that the semiconductor industry names the technology nodes of logic products (MPU\/ASIC) and non-volatile memory (Flash) differently. For quite a long time, the former used half pitch of the contacted metal line, and the latter used half pitch of uncontacted poly (floating gate). The physical Lg of the former is actually smaller than the node number, while the SL\/BL in the latter has a larger Lg than the node number. [2]
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4) New structure: However, the definition in 3) has changed in recent years as new devices have entered the market, such as FINFET and 3D NAND. In the example of the 14\/16nm FINFET process given in 2), the half pitch of the contacted metal line is 2⑧nm instead of the nominal 14\/16nm. The node name for 3D NAND has been changed to minimum array half pitch, which is approximately 8 nm. [1]
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5) Estimation: Due to the differences between the nominal node number and the actual process parameters, as well as the differences between the names of various companies, it is easy to cause confusion, so ASML gives an estimation formula, which can calculate a number similar to the nominal node number according to the actual process parameters of various companies, and is currently widely used in the industry. [3]
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6) Advanced degree: At present, there are large differences in the structure of the two chips, and each has its own evaluation methods, so it is not possible to say who is more advanced in the process technology, can only say that they are pursuing more extreme performance on their own road.
Storing special dram, the further down it gets harder. The first is the limitation of the process, and the process of mass production can be as small as it is small. But the memory chip is not good, the capacitor is large, sa these things have to be accurate. Small is not the most important thing.
Secondly, the integration of logic chips is relatively lower, and the output is certainly higher in the same case.
The third is that the error room of the logic chip is relatively large, small and fast is enough, the storage eats accuracy, and the process does not dare to do so.