1, because of the existence of electron tunneling effect, the accepted limit of crystal control range is 5nm. According to quantum forceAccording to scientific calculation, when the line width of the silicon chip is less than about 10nm, the possible line width limit is currently expected to be 1~10nm, not less than one nanometer. Chip manufacturers may be most concerned about the cost problem, "the end of Moore's law is not a technical problem, but an economic problem."
2, the improvement of the process process determines the size of the horizontal area of the 3D transistor. Without destroying the silicon atoms themselves, there is a theoretical limit to chip manufacturing, at about 0.5nm, because the silicon atoms themselves must maintain a certain distance between them. The manufacturing process is usually what we call the "manufacturing process of the CPU."Refers to the fineness of integrated circuits in the production process of cpus, that is, the higher the precision, the more advanced the production process.
3, usually said 5nm or 7nm is the width of the transistor (also called line width). The lowest layer of the chip is the mos tube, the smaller the feature size, the smaller the mos tube produced, which means the higher the integration of the chip, and then the cost is reduced. Under the condition that the chip occupies the same area, the higher the integration, the more functional circuits can be crammed into the chip.
4, if it is lower than 2nm, it is that the industry should have revolutionary inventions and theoretical improvements, which isMaybe even more elaborate. Therefore, when the process breaks through the physical limit, and then want to seek new manufacturing technology can not simply reduce the grid length from the article, after all, has been small to 7nm, and then add a variety of other auxiliary devices to reduce the leakage problem will not be worth the loss.
5, the diameter of silicon atoms is 5 nanometers, progress in the process has been difficult, the reason for improving the process is to reduce the cost, so that a single wafer can produce more chips. Materials other than silicon can be used, and in 2006 IBM silicon-germanium chips ran at 500GHz, which could not be popularized in the civilian field due to cost reasons. <6, nm heating is so bad because the more advanced the process technology, the smaller the diameter of the transistor on the chip, the more the number of transistors can be integrated, so bad. The more heat, of course, the more advanced the performance, and the 5 nanometer processor is already a very advanced process technology. Therefore, the number of integrated transistors is very large, and the heat of these transistors is very large.
1, nm chip is not the limit. 1nm is the molar limit, which isThe ultimate accuracy of silicon-based chips can only reach 1nm in theory, but due to the limitations of the natural environment, its actual accuracy can never reach 1nm. The smaller the process, the smaller the power consumption, in the case of achieving the same function, the heat is small, and the battery can be used for a longer time. This is the main reason why chip manufacturing processes are getting smaller and smaller.
2, the nano (nm) chip is the smallest size that can be achieved by semiconductor manufacturing technology, which represents the limit of microelectronics technology. The reason why 1 nanometer chip is considered the limit of microelectronics technology is because at this size, it is very difficult to manufacture due to the existence of physical limitationsLarge. At sizes below 1 nanometer, the behavior of electrons becomes increasingly difficult to predict and control, which leads to many problems in the manufacturing process, such as leakage current, thermal runaway, and so on.
3, nm chip is not the limit depends on the specific development of the chip industry. Generally speaking, 1nm chips are the limit. The manufacturing process of the chip is to inject transistors into the silicon-based material, the more transistors the stronger the performance, want to improve the chip process, it is necessary to increase the number of transistors per unit chip area.
4, the theoretical limit of the chip: the limit size of the silicon transistor is about 1 nanometer, which isAfter breaking through the physical limit, chip a few nanometers is the limit , and then want to seek new manufacturing technology can not simply reduce the grid length from the chip a few nanometers is the limit , after all, it has been as small as 7nm, Adding a variety of its chips a few nanometers is the limit his auxiliary devices to reduce the leakage problem will also be more than worth the loss. In this case, it is only possible to start from the material, change the characteristics by changing the material, and then make a breakthrough.
2, because the current coreThe mode of chip operation is still classical logic circuit. When the process is smaller than 5nm, quantum effects dominate.
The main difference between 3 nm and 7 nm is transistor density. The former has more than 700 million transistors per square millimeter, 80% higher than 7nm. Hard numbers are hard to understand. In simple terms, 7nm can accommodate three G76 cores, and now it can accommodate five. Another improvement is the optimization of performance and power consumption.
2, in my opinion, if it is below 2nm, or if it is found to 1nm, it is likely to reach the limitMHM. It is likely that people will no longer need a lower nm grade, but find another material. But at present, there is no better material than silicon, more suitable for mass production and use of semiconductors. If it is lower than 2nm, it is that the industry should have revolutionary inventions and theoretical improvements, which can be more refined.
3, the nm process is the physical limit of the chip process, the width of the semiconductor effect transistor body. This value is the most critical indicator of the chip market, and the specific data value represents each continuous improvement.
4, the successful application of nm process represents China semiconductorThe 7nm process has made breakthrough progress, which also marks the rise of China's semiconductor technology. In the field of semiconductors, the smaller the number of processes, the more advanced the technology. 7nm and below processes are advanced semiconductor processes and are the technical threshold to achieve high-end smartphone SOC (system on chip).
5. In addition, the breakthrough architecture and technology associated with it, as well as the future planning, were disclosed one by one. In terms of process nodes, Pat Kissinger announced that performance per watt will be the key indicator to measure the evolution of process nodes, which is because of the importance of semiconductor productionIn terms of product, PPA (performance, power and area, performance, power consumption, area) is a very important indicator.
The minimum CPU process technology is currently 10 nm. Usually CPU refers to the chip used in the computer, and the minimum manufacturing process is represented by Intel, which is the 10 nanometer process used in the Core 12. At present, the smallest manufacturing process in the chip industry is actually the mobile phone chip, which can be mass-producedIn terms of chips, it is the Snapdragon 8gen1 chip produced by Samsung in South Korea for Qualcomm Snapdragon in the United States, which uses a 4-nanometer process.
At present, the mature commercial only 14nm, in the future is 7nm, and then it is hard to say, too small, there is an electronic tunnel effect.
Therefore, it is currently expected that the possible line width limit is 1~10nm, not less than one nanometer.
IBM research said that the current most advanced technology can make 10 nanometer chips, but the use of silicon germanium to make transistor channels and EUV lithography, can reduce the size of the transistor by half, while still able toEnough to increase circuit power efficiency by 50%. However, EUV is particularly sensitive to vibration and the production process is very precise, so mass production will be difficult and the price will be very high.